1. Field of the Invention
The present invention relates to a method of analog/digital conversion in an analog/digital converter used in a pulse height analyzer for measuring a spectrum of pulse heights and the like in the field of radiation instrument technology in the nuclear industry, medical sciences and the like. More particularly, the present invention relates to a method of conversion in a so-called Wilkinson type (counting type) analog/digital converter for holding analog data inputted by a pulse-height-to-time converting means and then discharged at a constant current so as to obtain a time signal which is proportional to a magnitude of the analog data and for counting a number of pulses in a pulse line, obtained by gating clock pulses by the time signal, using a counter so as to obtain digital data outputs corresponding to the input analog data. Even more particularly, the present invention relates to a method of conversion in an analog/digital converter comprising a peak-holding circuit for holding a peak voltage of the inputted analog data, a peak-time detecting circuit for detecting a peak time when the input analog data reaches a peak voltage, a constant-current discharge circuit for discharging, at a constant current, the peak voltage held in the peak-holding circuit from a point of time when the peak time is detected by means of the peak-time detecting circuit, a zero-time detecting circuit for detecting a zero time when a voltage held in the peak-holding circuit is reduced to zero, and a time-to-digital converting circuit for counting a number of pulses in a pulse line, obtained by gating clock pulses from the point of time when the peak time is detected by the peak-time detecting circuit until the point of time when the zero time is detected by the zero-time detecting circuit, using a counter to output digital data corresponding to the input analog data.
2. Description of the Prior Art
In general, a Wilkinson type (counting type) analog/digital converter (hereinafter called an ADC for short) having superior characteristics in differential linearity has been mainly used as an ADC for use in a pulse height analyzer used in the above described fields since, of the various required characteristics, a superior uniformity of width occupied by each channel (a digitalized value is called a channel) is particularly required.
The conventional counting type ADC has a construction as shown in FIG. 7, which is a block diagram, and FIG. 8 which consists of timing charts of signals for each part of FIG. 7.
That is to say, referring not to FIG. 7, reference numeral 1 designates an input terminal in which analog data (1) is input. Numeral 2 designates a peak-holding circuit including a differential amplifier A, a diode D, a charging/discharging capacitor C.sub.H and the like therein. Numeral 3 designates a peak-time detecting circuit for detecting a point of time, when the input analog data (1) reaches a peak voltage, on the basis of an output voltage (3) of the differential amplifier A and for outputting a peak-time detecting signal (4) corresponding thereto. Numeral 4 designates a constant-current discharging circuit for closing a switch S by an order from a control circuit 6 at the point of time that the peak time is detected by the peak-time detecting circuit 3 so as to discharge the peak voltage held in the charging/discharging capacitor C.sub.H in the peak-holding circuit 2. Numeral 5 designates a zero-time detecting circuit for detecting a point of time when a voltage (2) held in the charging/discharging capacitor C.sub.H in the peak-holding circuit 2 is reduced to zero, (zero time) and for outputting a zero-time detecting signal (5) corresponding thereto. Numeral 7 designates a time-to-digital converting circuit comprising a clock generator 7A for generating clock pulses, a clock gate circuit which is 7B maintained in an enabled condition by means of the control circuit 6 so that the clock pulses may be passed therethrough from the clock generator 7A only for a period of time from the point of time when the peak is detected to the point of time when the zero time is detected, and a counter 7C for counting a number of pulses in a pulse line (6) output from the clock gate circuit 7B so as to output digital data corresponding to the input analog data (1).
That is to say, as obvious from timing charts of signals for each part as shown in FIG. 8, this counting type ADC detects the peak time of the input analog data (1) by means of the peak-time detecting circuit 3 on the basis of a change in the output voltage (3) from the differential amplifier A in the peak-holding circuit 2 to obtain the peak-time detecting signal (4) as the time signal, and detects the point of time when the voltage (2) charged in the charging/discharging capacitor CHR is reduced to zero so as to obtain the zero-time detecting signal (5) by discharging the peak voltage held in the charging/discharging capacitor C.sub.H in the peak-holding circuit 2 by means of the constant current discharging circuit 4 for a period of time proportional to the peak value of the input analog data (1) at a constant current I, and feeds the pulse line (6) having a number of pulses proportional to a magnitude (peak value) of the input analog data (1) into the counter 7 so as to obtain digital data corresponding to the input analog data (1) by controlling the clock gate 7B on the basis of the peak-time detecting signal (4) and the zero-time detecting signal (5).
However, a counting type ADC having the above described construction has shown the following problems.
That is to say, as obvious from the timing charts as shown in FIG. 8, it is found from the detailed investigation of a change in the voltage (2) due to the constant current discharge of the charging/discharging capacitor CH in the peak-holding circuit 2 that although ideally speaking, a waveform as shown by the dotted line should be obtained, in fact the output (3) of the differential amplifier A in the peak-holding circuit 2 is influenced by the capacity of the diode D and other stray capacities C.sub.s (shown in the drawing by a dotted line, so that a nonlinear portion, as shown in the drawing, is produced for a very short period of time from the point of time when the discharge is begun (this is deemed as a settling time of the peak-holding circuit 2) and as a result, the zero-time detecting signal (5) rises faster than in the original case and a period of time during which the clock gate circuit 7B is enabled is shortened, whereby the number of pulses in the input pulse line (6) input to the counter 7C is reduced. Thus, the digital data output from the time-to-digital converting circuit 7 is reduced to a value which is lower than the original desired value.
As shown in FIG. 9, which is an input-output characteristic diagraph, a problem of this nonlinear portion leads to not only a general deterioration of an accuracy of conversion but also the generation of the zero-time detecting signal (5) in the vicinity of the nonlinear portion, particularly in the case where the input analog signal is small, so that a very large error appears.